Cryptolets Tutorial at ISCA 2026

Cryptolets: Building a Community and Open-Source Hardware Repository for Cryptographic Computing

Event: ISCA 2026 Tutorial
Date: June 27, 2026 (Saturday afternoon, half day)
Location: ISCA 2026 Conference Venue, Room 301B

Schedule

What is Cryptolets?

Cryptolets is an NSF CIRC Grand project building an open hardware ecosystem for cryptographic computing, including zero-knowledge proofs and fully homomorphic encryption.

Why Cryptolets?

Cryptographic computing enables strong guarantees for privacy, integrity, and verifiability, but current systems are often too slow and too hard to build. Cryptolets lowers the barrier to entry with reusable hardware building blocks, chiplet-aware design flows, and shared evaluation infrastructure.

What this tutorial covers

• The Cryptolets vision and how to get involved
• Open-source hardware IP and chiplet-aware design and EDA workflows
• Benchmarking and verification infrastructure for reproducible comparisons
• Modular, extensible accelerators rather than one-off bespoke designs

Speaker Abstracts

Introducing Cryptolets

Brandon Reagen: In this talk I will introduce the Cryptolets program, goals, and initial accomplishments. I will explain ways to get involved and showcase initial development on modular functional units and point addition.

An Open-Source and Synthesizable SystemC UCIe Interface for Connecting Cryptolet Chiplets

Thierry Tambe and Rishabh Sharad Pomaje: Chiplet-based architectures offer a modular path to improved performance, energy efficiency, scalability, and manufacturing yield by enabling heterogeneous systems to be composed from reusable, specialized dies. The Universal Chiplet Interconnect Express (UCIe) standard is a key enabler of this paradigm, providing an open and interoperable die-to-die interface for chiplets from diverse vendors. However, most available UCIe IP remains commercial and closed source. We present an open-source, UCIe 2.0-compliant SystemC prototype for rapid synthesis of UCIe digital controllers and system-level chiplet evaluation. The prototype supports custom, vendor-defined streaming protocols, providing a practical foundation for exploring next-generation modular architectures.

Zero Knowledge Proofs

David Inyangson: Abstract to be announced.

A Chiplet Interface Model for System-Level PPA Exploration

Austin Rovinski: State-of-the-art cryptographic hardware accelerators often require a huge amount of silicon area, sometimes exceeding what can fit on a single chip. This motivates chiplet-based systems, where multiple chips are tightly integrated in one package instead of relying on one large die. In this talk, Austin Rovinski will present recent work on an automated interconnect modeling framework that simplifies chiplet interconnect modeling and enables rapid, system-level design space exploration for generic chiplet systems. A demonstration of the framework will follow later in the session.

Automated, Scalable, and End-to-End Formal Hardware Verification

Caroline Trippel: A 2024 Siemens EDA study found that even though verification consumed more than 50% of development resources, critical bugs still escaped to silicon in more than 85% of the studied industrial hardware design projects, indicating that verification is a major bottleneck. This 20-year low in first-silicon success coincides with a near-doubling of projects featuring AI accelerators, reaching 59% since 2022. These findings reflect the proliferation of hardware accelerators whose increasing variety and complexity exacerbate the challenge of traditional verification. This talk will challenge the conventional wisdom that rigorous formal verification is a manual task reserved for experts and introduce new approaches and tools we are developing to automate, scale, and democratize formal hardware verification.

Code generation for cryptographic kernels using multi-word modular arithmetic

Naifeng Zhang: Fully homomorphic encryption and zero-knowledge proofs are emerging as solutions for data security in distributed environments. However, widespread adoption is hindered by significant computational overhead from core cryptographic operations involving large integer arithmetic. This work presents a formalization of multi-word modular arithmetic (MoMA), which breaks down large bit-width integer arithmetic into operations on machine words. We further develop a rewrite system that implements MoMA through recursive rewriting of data types for compatibility with compiler infrastructures and code generators. We evaluate MoMA by generating cryptographic kernels, including BLAS operations and the number theoretic transform, targeting multiple GPUs. Our MoMA-based BLAS operations outperform state-of-the-art multi-precision libraries by orders of magnitude, and MoMA-based NTTs achieve near-ASIC performance on commodity GPUs.

The Cryptolets Design Challenge

Warren Savage: I will explain the challenge and how you can get access to free silicon.

Demo and question and answer session

Code and Demo (Alhad Daftardar, Gaurav Kuwar, Zhengping Zhu): Live code demo followed by Q&A.

Organizers

• Warren Savage (Rocksavage Technology)
• Brandon Reagen (NYU)
• Siddharth Garg (NYU)
• Austin Rovinski (NYU)
• Ramesh Karri (NYU)
• Caroline Trippel (Standford)
• Thierry Tambe (Stanford)
• Tushar Jois (CUNY)
• Rosario Gennaro (CUNY)
• Alhad Daftardar (NYU)
• Gaurav Kuwar (Capital One)
• Jianqiao Mo (Website Support, NYU)

For more details, contact the organizers or visit ISCA 2026.