Speaker Series
Talks and invited speakers hosted by Cryptolets
You can also watch past talks on the YouTube playlist.
Speaker Series Talk 06
Speaker: Prof. Siddharth Garg (NYU)
Title: High(er)-Level Synthesis: Agentic AI for Complex Hardware Design
Date: September 9, 2026 @ 3:00 PM EDT
Zoom: Join the talk on Zoom
Abstract: High-Level Synthesis (HLS) has raised the abstraction level of hardware design, but building high-performance accelerators still requires substantial hardware expertise. This challenge becomes especially acute for complex cryptographic protocols, where implementations may involve large arithmetic kernels, intricate control and data movement, rapidly evolving algorithms, and demanding performance and security constraints.
In this talk, I will discuss our recent work on using large language models and reasoning agents to further raise the abstraction level of HLS. We explore how AI can transform software into synthesizable implementations, reason about hardware-oriented code transformations, introduce and tune HLS directives, and iteratively improve designs using feedback from synthesis tools. We then move toward agentic HLS flows in which reasoning models interact with compilers, synthesis tools, and optimization techniques to explore implementations rather than simply generate code in a single pass.
I will use complex cryptographic protocols as a motivating case study for what these capabilities could enable. Emerging protocols, from zero-knowledge proofs and fully homomorphic encryption to post-quantum cryptography, contain sophisticated computations that are difficult to translate into efficient hardware by hand. AI-assisted HLS offers the possibility of turning high-level algorithmic descriptions into specialized architectures while automatically navigating transformations, parallelism, memory organization, and performance-area tradeoffs.
More broadly, these results point toward an AI-native hardware design methodology in which designers increasingly specify algorithms, constraints, and intent, while intelligent agents collaborate with established EDA tools to construct and optimize the implementation. I will discuss the limitations of today's models, why grounding in compiler and synthesis feedback is essential, and what will be required before such systems can reliably build the complex hardware underlying future cryptographic and computing systems.
Speaker Series Talk 05
Speaker: Prof. Tushar Jois (City College of New York / CUNY Graduate Center)
Title: ThriftyMPC: Reducing the Cost of Large-Scale MPC in the Cloud
Date: August 12, 2026
Paper: IACR ePrint 2026/977
Abstract: Cloud computing has become the standard for large-scale computation, offering elastic scalability and on-demand resources that exceed typical on-premise capabilities. However, many large-scale computations over sensitive data, such as genome-wide association studies (GWAS), face significant barriers to cloud adoption due to privacy concerns and regulatory constraints. While cryptographic primitives like multi-party computation can alleviate these concerns through provable privacy guarantees, their substantial communication and computational overhead can make cloud deployment cost-prohibitive. To address both privacy and cost constraints, we present ThriftyMPC. ThriftyMPC is a framework that leverages spot instances, ephemeral cloud compute at reduced rates, to enable cost-effective, privacy-preserving computation at scale by combining secure multi-party computation with preemption-tolerant execution. We introduce a formal model for multi-party execution under ephemeral compute conditions, demonstrate how ThriftyMPC handles spot instance preemptions while maintaining cryptographic security guarantees, and provide a formal discussion of these guarantees. Our evaluations on realistic GWAS-inspired workloads over the Google Cloud Platform demonstrate robust execution despite spot instance churn, and show significant cost reduction compared to the state-of-the-art multi-party computation framework, MP-SPDZ, run traditionally using on-demand instances. We show that leveraging multi-party computation on spot instances makes privacy-preserving computation economically viable, enabling organizations to harness the cloud for sensitive workloads previously confined to isolated, on-premise deployments.
Speaker Series Talk 04
Speaker: Prof. Rosario Gennaro (CUNY)
Title: Towards Verifiable AI with Lightweight Cryptographic Proofs of Inference
Date: July 8, 2026 @ 3:00 PM EDT
Abstract: When large AI models are deployed as cloud-based services, clients have no guarantee that responses are correct or were produced by the intended model. Running inference locally is often infeasible for large models, and existing cryptographic proof systems, while offering strong correctness guarantees, introduce prohibitive prover overhead. This talk presents a verifiable inference framework that replaces full cryptographic proofs with a lightweight sampling-based approach grounded in statistical properties of neural networks. The prover commits to the execution trace of inference via Merkle-tree-based vector commitments and opens only a small number of entries along randomly sampled paths from output to input. The resulting protocol trades soundness for efficiency, making it well-suited to auditing and large-scale deployment settings where repeated queries amplify detection probability. Experimental results show several orders of magnitude reduction in proving time compared to state-of-the-art cryptographic proof systems, while maintaining practical verification guarantees.
Speaker Series Talk 03
Speaker: Prof. Austin Rovinski (NYU)
Title: An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
Date: June 10, 2026 @ 3:00 PM EDT
Abstract: State-of-the-art cryptographic hardware accelerators often require a huge amount of silicon area, sometimes exceeding what can fit on a single chip. This motivates chiplet-based systems, where multiple chips are tightly integrated in one package instead of relying on one large die. In this talk, Austin Rovinski will present recent work on an automated interconnect modeling framework that simplifies chiplet interconnect modeling and enables rapid, system-level design space exploration for cryptographic chiplet systems, or cryptolets. The talk will also include a sneak-peek demo of the framework ahead of its open-source release next month.
Speaker Series Talk 02
Speaker: Prof. Brandon Reagen (NYU)
Title: The Cryptolets Program with Applications to Point Addition
Date: May 13, 2026 @ 3:00 PM EDT
Abstract: Cryptographic computing is changing what we can compute and how we think about data sharing. Methods including fully homomorphic encryption and zero-knowledge proofs have gained attention and are starting to be deployed, but high performance overheads still limit ubiquity. Cryptolets supports this growing area by developing an open-source hardware IP repository spanning modular multipliers to full accelerators such as NTT and MSM units. The program also goes beyond an IP library by building open-source chiplet interfaces for scale-out acceleration and tightly integrating formal verification to prove design correctness. This talk reviews those efforts and highlights early library developments for point addition and MSM, which are commonly used in ZKPs.
Speaker Series Talk 01
Speaker: Prof. Ramesh Karri (NYU)
Title: LLM4PQC: LLM-Driven High-Level Synthesis for Post-Quantum Cryptography Hardware
Date: April 8, 2026 @ 3:00 PM EDT
Abstract: Designing hardware accelerators for post-quantum cryptography (PQC) is labor-intensive, with a critical bottleneck being the manual refactoring of NIST PQC reference C code into HLS-ready specifications. We present LLM4PQC, an agentic LLM-based framework that automates this conversion, generating synthesizable HLS C code for complex PQC primitives including NTT accelerators and wide memory interfaces. The framework employs a feedback-driven, hierarchical verification pipeline spanning C compilation, C simulation, and RTL simulation to ensure functional correctness. Preliminary case studies on NIST PQC reference designs, including Kyber, Dilithium, and Falcon, demonstrate significant reductions in manual effort and faster design-space exploration relative to traditional flows. LLM4PQC offers a scalable and efficient pathway for accelerating the hardware realization of next-generation cryptographic standards.