Speaker Series
Talks and invited speakers hosted by Cryptolets
Speaker Series Talk 03
Speaker: Prof. Austin Rovinski (NYU)
Title: An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
Date: June 10, 2026 @ 3:00 PM EDT
Zoom: Join the talk on Zoom
Abstract: State-of-the-art cryptographic hardware accelerators often require a huge amount of silicon area, sometimes exceeding what can fit on a single chip. This motivates chiplet-based systems, where multiple chips are tightly integrated in one package instead of relying on one large die. In this talk, Austin Rovinski will present recent work on an automated interconnect modeling framework that simplifies chiplet interconnect modeling and enables rapid, system-level design space exploration for cryptographic chiplet systems, or cryptolets. The talk will also include a sneak-peek demo of the framework ahead of its open-source release next month.
Speaker Series Talk 02
Speaker: Prof. Brandon Reagen (NYU)
Title: The Cryptolets Program with Applications to Point Addition
Date: May 13, 2026 @ 3:00 PM EDT
Abstract: Cryptographic computing is changing what we can compute and how we think about data sharing. Methods including fully homomorphic encryption and zero-knowledge proofs have gained attention and are starting to be deployed, but high performance overheads still limit ubiquity. Cryptolets supports this growing area by developing an open-source hardware IP repository spanning modular multipliers to full accelerators such as NTT and MSM units. The program also goes beyond an IP library by building open-source chiplet interfaces for scale-out acceleration and tightly integrating formal verification to prove design correctness. This talk reviews those efforts and highlights early library developments for point addition and MSM, which are commonly used in ZKPs.
Speaker Series Talk 01
Speaker: Prof. Ramesh Karri (NYU)
Title: LLM4PQC: LLM-Driven High-Level Synthesis for Post-Quantum Cryptography Hardware
Date: April 8, 2026 @ 3:00 PM EDT
Abstract: Designing hardware accelerators for post-quantum cryptography (PQC) is labor-intensive, with a critical bottleneck being the manual refactoring of NIST PQC reference C code into HLS-ready specifications. We present LLM4PQC, an agentic LLM-based framework that automates this conversion, generating synthesizable HLS C code for complex PQC primitives including NTT accelerators and wide memory interfaces. The framework employs a feedback-driven, hierarchical verification pipeline spanning C compilation, C simulation, and RTL simulation to ensure functional correctness. Preliminary case studies on NIST PQC reference designs, including Kyber, Dilithium, and Falcon, demonstrate significant reductions in manual effort and faster design-space exploration relative to traditional flows. LLM4PQC offers a scalable and efficient pathway for accelerating the hardware realization of next-generation cryptographic standards.